The invention relates generally to the field of semiconductor manufacturing and more specifically to wells under a trench isolation layer.
For electrostatic discharge (ESD) protection circuit, high value resistors are often required. In order to achieve such resistance values, well resistors, formed from implanted well regions underneath thin isolation layers, are often used. These well regions exhibit a characteristic sheet resistance, typically defined in units of ohms per square. Typically, well resistor layouts are formed in a rectangular shape. The length to width ratio of each resistor is chosen based upon the targeted total resistance value. Length is defined as the dimension parallel to the current flow, width is the dimension perpendicular to the current flow. The minimum width of each resistor is chosen in order to attain repeatable well sheet resistance. By increasing the resistivity of the well region the area of the resistor could decrease thereby saving a significant amount of real estate of the integrated circuit, which leads to cost savings. One way to increase the resistivity is to perform multiple ion implantation steps using various well doses for different regions of the integrated circuit. However, this results in additional patterning and masking steps, thereby, increasing cycle time and cost of manufacturing. Therefore, there is a need for a process that increases the resistivity of the well region without increasing cycle time and cost.